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| this is information on a product in full production. july 2016 docid025146 rev 6 1/135 stm32f301x6 stm32f301x8 arm ? cortex ? -m4 32-bit mcu+fpu, up to 64 kb flash, 16 kb sram, adc, dac, comp, op-amp, 2.0 ? 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m4 cpu with fpu (72 mhz max.), single-c ycle multiplication and hw division, dsp instruction ? memories ? 32 to 64 kbytes of flash memory ? 16 kbytes of sram on data bus ? crc calculation unit ? reset and power management ?v dd , v dda voltage range: 2.0 to 3.6 v ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low-power: sleep, stop, and standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x 16 pll option ? internal 40 khz oscillator ? up to 51 fast i/o por ts, all mappable on external interrupt vectors, several 5 v-tolerant ? interconnect matrix ? 7-channel dma controller supporting timers, adcs, spis, i 2 cs, usarts and dac ? 1 adc 0.20 s (up to 15 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, single ended/differential mode, separate analog supply from 2.0 to 3.6 v ? temperature sensor ? 1 x 12-bit dac channel with analog supply from 2.4 to 3.6 v ? three fast rail-to-rail analog comparators with analog supply from 2.0 to 3.6 v ? 1 x operational amplifier that can be used in pga mode, all terminal accessible with analog supply from 2.4 to 3.6 v ? up to 18 capacitive sensing channels supporting touchkey, linear and rotary sensors ? up to 9 timers ? one 32-bit timer with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? one 16-bit 6-channel advanced-control timer, with up to 6 pwm channels, deadtime generation and emergency stop ? three 16-bit timers with ic/oc/ocn or pwm, deadtime gen. and emergency stop ? one 16-bit basic timer to drive the dac ? 2 watchdog timers (independent, window) ? systick timer: 24-bit downcounter ? calendar rtc with ala rm, periodic wakeup from stop/standby ? communication interfaces ? three i2cs with 20 ma current sink to support fast mode plus ? up to 3 usarts, 1 with iso 7816 i/f, auto baudrate detect and dual clock domain ? up to two spis with mu ltiplexed full duplex i2s ? infrared transmitter ? serial wire debug (swd), jtag ? 96-bit unique id table 1. device summary reference part number stm32f301x6 stm32f301r6, stm32f301c6, stm32f301k6 stm32f301x8 stm32f301r8, stm32f301c8, STM32F301K8 lqfp48 (7x7 mm) lqfp64 (10x10 mm) ufqfpn32 (5x5 mm) wlcsp49 (3.417x3.151 mm) www.st.com
contents stm32f301x6 stm32f301x8 2/135 docid025146 rev 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm ? cortex ? -m4 core with fpu, embedded flash and sram . . . . . . . 13 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 14 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 19 3.11 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 ultra-fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.1 advanced timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.2 general-purpose timers (tim2, tim15, tim16, tim17) . . . . . . . . . . . . . 23 3.15.3 basic timer (tim6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 docid025146 rev 6 3/135 stm32f301x6 stm32f301x8 contents 4 3.15.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24 3.17 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 27 3.19 serial peripheral interfaces (spi)/inter-integrated sound interfaces (i2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.21 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.22 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.22.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 58 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 58 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 contents stm32f301x6 stm32f301x8 4/135 docid025146 rev 6 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.16 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.18 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.21 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.1 wlcsp49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.2 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.3 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.5.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.5.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 130 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 docid025146 rev 6 5/135 stm32f301x6 stm32f301x8 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f301x6/8 device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. external analog supply values for analog peripheral s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. stm32f301x6/8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. stm32f301x6/8 i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. stm32f301x6/8 spi/i2s implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. capacitive sensing gpios available on stm32f30 1x6/8 devices . . . . . . . . . . . . . . . . . . . 29 table 11. no. of capacitive sensing channels available on stm32f301x6/8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. stm32f301x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. alternate functions for port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15. alternate functions for port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16. alternate functions for port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17. alternate functions for port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 18. alternate functions for port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. stm32f301x6 stm32f301x8 peripheral register boundary addresses . . . . . . . . . . . . . . 50 table 20. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 21. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 22. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 23. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 24. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 25. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 table 28. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 29. typical and maximum current consumption fr om vdd supply at vdd = 3.6v . . . . . . . . . . 61 table 30. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 63 table 31. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 63 table 32. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 64 table 33. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 64 table 34. typical current consumption in run mode, code with data processing running from flash 66 table 35. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 67 table 36. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 37. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 38. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 39. wakeup time using usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 40. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 41. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 42. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 43. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 44. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 46. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 list of tables stm32f301x6 stm32f301x8 6/135 docid025146 rev 6 table 48. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 49. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 50. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 51. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 52. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 53. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 54. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 55. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 56. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 57. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 58. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 59. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 60. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 61. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 63. i2s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 64. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 65. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 66. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 table 67. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 68. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 69. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 70. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 71. operational amplifier characteristic s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 72. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 73. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 74. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 75. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 76. wlcsp49 recommended pcb design rules (0.4 mm pi tch) . . . . . . . . . . . . . . . . . . . . . . 118 table 77. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 78. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 79. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 80. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 81. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 82. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 docid025146 rev 6 7/135 stm32f301x6 stm32f301x8 list of figures 8 list of figures figure 1. stm32f301x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4. stm32f301x6/8 ufqfn32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5. stm32f301x6/8 lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. stm32f301x6/8 lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. stm32f301x6/8 wlcsp49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. stm32f301x6/8 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 65 figure 14. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 18. hsi oscillator accuracy char acterization results for soldered parts . . . . . . . . . . . . . . . . . . 79 figure 19. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 20. tc and tta i/o input characteri stics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 21. five volt tolerant (ft and ftf) i/o input char acteristics - cmos port. . . . . . . . . . . . . . . . . 86 figure 22. five volt tolerant (ft and ftf) i/o input charac teristics - ttl port . . . . . . . . . . . . . . . . . . . 87 figure 23. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 24. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 25. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 26. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 27. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 28. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 29. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30. adc typical current consumption in single-end ed and differential modes . . . . . . . . . . . . 101 figure 31. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 32. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 33. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 34. maximum v refint scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 35. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 36. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 37. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 38. wlcsp49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 39. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 119 figure 40. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 41. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 42. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 122 figure 43. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 44. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 list of figures stm32f301x6 stm32f301x8 8/135 docid025146 rev 6 figure 45. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 46. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 47. ufqfpn32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 docid025146 rev 6 9/135 stm32f301x6 stm32f301x8 introduction 51 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f301x6/8 microcontrollers. this datasheet should be read in conjunction with the stm32f301x6/8 and stm32f318x8 advanced arm ? -based 32-bit mcus reference manual (rm0366). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from arm website www.arm.com. description stm32f301x6 stm32f301x8 10/135 docid025146 rev 6 2 description the stm32f301x6/8 family is based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 72 mhz and embedding a floating point unit (fpu). the family incorporates high-speed embedded memories (up to 64 kbytes of flash memory, 16 kbytes of sram), and an extens ive range of enhanced i/os and peripherals connected to two apb buses. the devices offer a fast 12-bit adc (5 msps), three comparators, an operational amplifier, up to 18 capacitive sensing channels, one dac channel, a low-power rtc, one general- purpose 32-bit timer, one timer dedicated to motor control, and up to three general-purpose 16-bit timers, and one timer to drive the dac. they also feature standard and advanced communication interfaces: three i 2 cs, up to three usarts, up to two spis with multiplexed full-duplex i2s, and an infrared transmitter. the stm32f301x6/8 family operates in the ?40 to +85c and ?40 to +105c temperature ranges from at a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f301x6/8 family offers devices in 32-, 48-, 49- and 64-pin packages. the set of included peripherals changes with the device chosen. docid025146 rev 6 11/135 stm32f301x6 stm32f301x8 description 51 table 2. stm32f301x6/8 device features and peripheral counts peripheral stm32f301kx stm32f301cx stm32f301rx flash (kbytes) 32 64 32 64 32 64 sram (kbytes) 16 timers advanced control 1 (16-bit) general purpose 3 (16-bit) 1 (32 bit) basic 1 systick timer 1 watchdog timers (independent, window) 2 pwm channels (all) (1) 16 18 pwm channels (except complementary) 10 12 comm. interfaces spi/i2s 2 i 2 c3 usart 2 3 dma channels 7 capacitive sensing channels 18 12-bit adc number of channels 1 8 1 11 1 15 12-bit dac channels 1 analog comparator 2 3 operational amplifier 1 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: - 40 to 85c / - 40 to 105c junction temperature: - 40 to 125c packages ufqfpn32 lqfp48, wlcsp49 lqfp64 1. this total number considers also the pw ms generated on the complementary output channels. description stm32f301x6 stm32f301x8 12/135 docid025146 rev 6 figure 1. stm32f301x6/8 block diagram 0 6 y 9 7 r x f k 6 h q v l q j & r q w u r o o h u $ + % g h f r g h u 7 , 0 ( 5 & k d q q h o v & r p s & k d q q h o % 5 . d v $ ) 7 , 0 ( 5 7 , 0 ( 5 3 : 0 8 6 $ 5 7 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) : l q : $ 7 & + ' 2 * % x v 0 d w u l [ ) 3 8 & r u w h [ 0 & 3 8 ) p d [ 0 + ] 1 9 , & * 3 ' 0 $ f k d q q h o v ) o d v k l q w h u i d f h 2 % / ) / $ 6 + . % e l w v - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 0 6 6 : ' , 2 - 7 ' 2 $ v $ ) 3 r z h u 9 r o w d j h u h j 9 w r 9 9 ' ' 6 x s s o \ 6 x s h u y l v l r q 3 2 5 3 ' 5 3 9 ' 3 2 5 5 h v h w , q w 9 ' ' , 2 w r 9 9 6 6 1 5 ( 6 ( 7 9 ' ' $ 9 6 6 $ , q g : ' * . 6 w d q g e \ l q w h u i d f h 3 / / # 9 ' ' , 2 # 9 ' ' $ ; 7 $ / 2 6 & 0 + ] 5 h v h w f o r f n f r q w u r o $ + % 3 & / . $ 3 % 3 & / . $ 3 % 3 & / . $ + % $ 3 % $ + % $ 3 % & 5 & $ 3 % ) p d [ 0 + ] $ 3 % i p d [ 0 + ] * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' 2 6 & b , 1 2 6 & b 2 8 7 6 3 , , 6 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 5 & / 6 7 , 0 ( 5 6 3 , , 6 e l w ' $ & , ) # 9 ' ' $ 7 , 0 ( 5 e l w 3 : 0 3 $ > @ 3 % > @ 3 & > @ 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) & k d q q h o v ( 7 5 d v $ ) ' $ & b & + d v $ ) + & / . ) & / . 8 6 $ 5 7 & / . 5 & + 6 0 + ] 6 5 $ 0 . % 6 : - 7 $ * 7 3 , 8 , e x v ' e x v 6 \ v w h p e l w $ ' & 7 h p s v h q v r u 9 5 ( ) 9 5 ( ) 7 , 0 ( 5 ( ; 7 , 7 : . 8 3 ; ; $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) * 3 , 2 3 2 5 7 ) 3 ' > @ 3 ) > @ , ) , & & / . $ ' & 6 $ 5 & / . # 9 ' ' , 2 # 9 ' ' $ # 9 6 : ; 7 $ / n + ] 2 6 & b , 1 2 6 & b 2 8 7 9 % $ 7 9 w r 9 5 7 & $ : 8 % d f n x s 5 h j % \ w h % d f n x s l q w h u i d f h $ 1 7 , 7 $ 0 3 , & , & 2 s $ p s # 9 ' ' $ , 1 [ [ 2 8 7 [ [ , 1 7 ( 5 ) $ & ( 6 < 6 & ) * & 7 / * 3 & r p s d u d w r u * 3 & r p s d u d w r u * 3 & r p s d u d w r u 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) # 9 ' ' $ ; [ , q v 2 8 7 v d v $ ) * u r x s v r i f k d q q h o v d v $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) , & docid025146 rev 6 13/135 stm32f301x6 stm32f301x8 functional overview 51 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu, embedded flash and sram the arm ? cortex ? -m4 processor with fpu is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 32-bit risc processor with fpu features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single-precis ion fpu speeds up software development by using metalanguage development tools while avoiding saturation. with its embedded arm core, the stm32f301x6/ 8 family is compatib le with all arm tools and software. figure 1 shows the general block diagram of the stm32f301x6/8 family devices. 3.2 memories 3.2.1 embedded flash memory all stm32f301x6/8 devices feature up to 64 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). 3.2.2 embedded sram stm32f301x6/8 devices feature 16 kbytes of embedded sram. 3.3 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10) and usart2 (pa2/pa3). functional overview stm32f301x6 stm32f301x8 14/135 docid025146 rev 6 3.4 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v ss , v dd = 2.0 to 3.6 v : external power supply for i/os and the internal regulator. it is provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog power supply for adc, dac, comparators, operational amplifier, reset blocks, rcs and pll. the mi nimum voltage to be applied to v dda differs from one analog peripheral to another. table 3 provides the summary of the v dda ranges for analog peripherals. the v dda voltage level must always be greater than or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rt c, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.5.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. table 3. external analog supply values for analog peripherals analog peripheral minimum v dda supply maximum v dda supply adc/comp 2.0 v 3.6 v dac/opamp 2.4 v 3.6 v docid025146 rev 6 15/135 stm32f301x6 stm32f301x8 functional overview 51 3.5.3 voltage regulator the regulator has three operation modes: main (mr), low-power (lpr), and power-down. ? the mr mode is used in the nominal regulation mode (run) ? the lpr mode is used in stop mode. ? the power-down mode is used in standby mo de: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. 3.5.4 low-power modes the stm32f301x6/8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external li nes, the pvd output, the rtc alarm, compx, i2c or usartx. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. functional overview stm32f301x6 stm32f301x8 16/135 docid025146 rev 6 note: for more details about the interconnect action s, please refer to the corresponding sections in the stm32f301x6/8 and stm32f318x8 reference manual rm0366. table 4. stm32f301x6/8 peripheral interconnect matrix interconnect source interconnect destination interconnect action timx timx timers synchronization or chaining adc1 dac1 conversion triggers dma memory to memory transfer trigger compx comparator output blanking compx timx timer input: ocref_clr input, input capture adc1 tim1 timer triggered by analog watchdog gpio rtcclk hse/32 mc0 tim16 clock source used as input channel for hsi and lsi calibration css cpu (hard fault) compx pvd gpio tim1 tim15, 16, 17 timer break gpio timx external trigger, timer break adc1 dac1 conversion external trigger dac1 compx comparator inverting input docid025146 rev 6 17/135 stm32f301x6 stm32f301x8 functional overview 51 3.7 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domain s. the maximum fr equency of the ah b and the high speed apb domains is 72 mhz, while the maximum allowe d frequency of the low speed apb domain is 36 mhz. the advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. to achieve audio class perfor mance, an audio crystal can be used. functional overview stm32f301x6 stm32f301x8 18/135 docid025146 rev 6 figure 2. clock tree 0 + ] + 6 ( 2 6 & 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 0 + ] + 6 , 5 & , : ' * & / . w r , : ' * 3 / / [ [ [ 3 / / 0 8 / 0 & 2 $ + % $ 3 % s u h v f d o h u + & / . 3 / / & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ / 6 ( / 6 , + 6 , + 6 , + 6 ( w r 5 7 & 3 / / 6 5 & 6 : 6 < 6 & / . 5 7 & & / . 5 7 & 6 ( / > @ w r 7 , 0 , i $ 3 % s u h v f d o h u [ h o v h [ ) / , 7 ) & / . w r ) o d v k s u r j u d p p l q j l q w h u i d f h w r , & [ [ w r 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . 0 6 9 w r , 6 [ [ w r f r u w h [ 6 \ v w h p w l p h u ) + & / . & r u w h [ i u h h u x q q l q j f o r f n w r $ 3 % s h u l s k h u d o v $ + % s u h v f d o h u & 6 6 / 6 ( 2 6 & n + ] / 6 , 5 & n + ] $ 3 % s u h v f d o h u , i $ 3 % s u h v f d o h u [ h o v h [ 3 & / . w r $ 3 % s h u l s k h u d o v 7 , 0 $ ' & 3 u h v f d o h u w r $ ' & $ ' & 3 u h v f d o h u , 6 6 5 & 6 < 6 & / . ( [ w f o r f n , 6 b & . , 1 [ 0 d l q f o r f n r x w s x w 3 / / & / . + 6 , + 6 ( 0 & 2 6 < 6 & / . / 6 , 3 / / 1 2 ' , 9 0 & 2 3 5 ( / 6 ( docid025146 rev 6 19/135 stm32f301x6 stm32f301x8 functional overview 51 3.8 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.9 direct memory access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrup ts when the controller reaches the end of the buffer. each of the 7 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, timers, dac and adc. 3.10 interrupts and events 3.10.1 nested vectored inte rrupt controller (nvic) the stm32f301x6/8 devices embed a nested vect ored interrupt controller (nvic) able to handle up to 60 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. functional overview stm32f301x6 stm32f301x8 20/135 docid025146 rev 6 3.11 fast analog-to-digital converter (adc) an analog-to-digital converter, with selectable resolution between 12 and 6 bit, is embedded in the stm32f301x6/8 family devices. the adc has up to 15 external channels performing conversions in single-shot or scan modes. channels can be configured to be either single- ended input or differential input. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? single-shunt phase current reading techniques. the adc can be served by the dma controller. three analog watchdogs are available. the analog watchdog feature allows very precise monitoring of the converted voltage of one, so me or all selected cha nnels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose ti mers (timx) and the advanced-control timer (tim1) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 3.11.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.11.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc1_in18 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memo ry area. it is accessible in read-only mode. docid025146 rev 6 21/135 stm32f301x6 stm32f301x8 functional overview 51 3.11.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.12 digital-to-analog converter (dac) one 12-bit buffered dac channel (dac1_out1) ca n be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supp orts the following features: ? one dac output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dma capability ? external triggers for conversion 3.13 operational amplifier (opamp) the stm32f301x6/8 devices embed one operatio nal amplifier with external or internal follower routing and pga capab ility (or even amplifier and f ilter capability with external components). when the operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8.2 mhz bandwidth ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to be 2, 4, 8 or 16. functional overview stm32f301x6 stm32f301x8 22/135 docid025146 rev 6 3.14 ultra-fast comparators (comp) the stm32f301x6/8 devices embed up to three ultra-fast rail-to-rail comparators which offer the features below: ? programmable internal or external reference voltage ? selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 27: embedded internal reference voltage for the value and precision of the internal reference voltage. all comparators can wake up from stop mode, and also generate interrupts and breaks for the timers. 3.15 timers and watchdogs the stm32f301x6/8 devices include advanced cont rol timer, up to general-purpose timers, basic timer, two watchdog timers and a systick timer. table 5 compares the features of the advanced control, general purpose and basic timers. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1 (1) 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim15 (1) 16-bit up any integer between 1 and 65536 yes 2 1 tim16 (1) , tim17 (1) 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6 16-bit up any integer between 1 and 65536 yes 0 no 1. tim1/15/16/17 can be clocked from the pll running at 144 mhz when the system clock source is the pll and ahb or apb2 subsystem clocks are not divided by more than 2 cumulatively. docid025146 rev 6 23/135 stm32f301x6 stm32f301x8 functional overview 51 3.15.1 advanced timer (tim1) the advanced-control timer can each be se en as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead- times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.15.2 using the same architecture, so t he advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.15.2 general-purpose timers (t im2, tim15, tim16, tim17) there are up to four synchronizable ge neral-purpose timers embedded in the stm32f301x6/8 devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. tim2 tim2 has a 32-bit auto-reload up/d owncounter and 32-bit prescaler it features 4 independent channels for input capture/output compar e, pwm or one-pulse mode output. it can work together, or with th e other general-purpose timers via the timer link feature for synchronization or event chaining. the counter can be frozen in debug mode. it has independent dma request generation and supports quadrature encoders. tim15, tim16 and tim 17 these three timers general-purpos e timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/ output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. functional overview stm32f301x6 stm32f301x8 24/135 docid025146 rev 6 3.15.3 basic timer (tim6) this timer is mainly used for da c trigger generation. it can also be used as a generic 16-bit time base. 3.15.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standb y modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option byte. the counter can be frozen in debug mode. 3.15.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.15.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.16 real-time clock (rtc ) and backup registers the rtc and the 20 backup registers are supplied through a switch that takes power from either the v dd supply when present or the vbat pin. the backup registers are five 32-bit registers used to store 20 byte of user application data when v dd power is not present. they are not reset by a system or power rese t, or when the device wakes up from standby mode. docid025146 rev 6 25/135 stm32f301x6 stm32f301x8 functional overview 51 the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap year), 30, and 31 days of the month. ? two programmable alarms with wake up fr om stop and standb y mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? two anti-tamper detection pins with prog rammable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. functional overview stm32f301x6 stm32f301x8 26/135 docid025146 rev 6 3.17 inter-integrated circuit interfaces (i 2 c) the devices feature three i 2 c bus interfaces which can oper ate in multimaster and slave mode. each i2c interface can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. all i 2 c interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, it provides har dware support for sm bus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. it also has a clock domain independent from the cpu clock, allowing the i2cx (x=1,3) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to table 7 for the features availabl e in i2c1, i2c2 and i2c3. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 7. stm32f301x6/8 i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 i2c3 7-bit addressing mode x x x 10-bit addressing mode x x x standard mode (up to 100 kbit/s) x x x fast mode (up to 400 kbit/s) x x x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x x x independent clock x x x smbus x x x wakeup from stop x x x docid025146 rev 6 27/135 stm32f301x6 stm32f301x8 functional overview 51 3.18 universal synchronous/asynch ronous receiver transmitter (usart) the stm32f301x6/8 devices have three em bedded universal synchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbit/s. all usarts support hardware management of the cts and rts signals, multiprocessor communication mode, single-wire half-duplex communication mode and synchronous mode. usart1 supports smartcard mode, irda sir endec, lin master capability and autobaudrate detection. all usart interfaces can be served by the dma controller. refer to table 8 for the features available in all usarts interfaces. 3.19 serial peripheral interface s (spi)/inter-in tegrated sound interfaces (i2s) two spi interfaces (spi2 and spi3) allow comm unication up to 18 mbit/s in slave and master modes in full-duplex and simplex modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. two standard i2s interfaces (multiplexed wit h spi2 and spi3) are available, that can be operated in master or slave mode. these interf aces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of th e i2s interfaces is/are configured in master table 8. usart features usart modes/features (1) 1. x = supported. usart1 usart2 usart3 hardware flow control for modem x x x continuous communication using dma x x x multiprocessor communication x x x synchronous mode x x x smartcard mode x - - single-wire half-duplex communication x x x irda sir endec block x - - lin mode x - - dual clock domain and wakeup from stop mode x - - receiver timeout interrupt x - - modbus communication x - - auto baud rate detection x - - driver enable x x x functional overview stm32f301x6 stm32f301x8 28/135 docid025146 rev 6 mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. refer to table 9 for the features available in spi2 and spi3. 3.20 touch sensing controller (tsc) the stm32f301x6/8 devices provide a simple solution for adding capacitive sensing functionality to any application. these device s offer up to 18 capacitive sensing channels distributed over 6 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (for example glass, plastic). the capacitive variation introduced by the finger (or any co nductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. to limit the cpu bandwidth usage th is acquisition is dire ctly managed by the hardware touch sensing controller and only r equires few external components to operate. table 9. stm32f301x6/8 spi/i2s implementation spi features (1) 1. x = supported. spi2 spi3 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x i2s mode x x ti mode x x docid025146 rev 6 29/135 stm32f301x6 stm32f301x8 functional overview 51 table 10. capacitive sensing gp ios available on stm32f301x6/8 devices group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 tsc_g1_io2 pa1 tsc_g1_io3 pa2 tsc_g1_io4 pa3 2 tsc_g2_io1 pa4 tsc_g2_io2 pa5 tsc_g2_io3 pa6 tsc_g2_io4 pa7 3 tsc_g3_io1 pc5 tsc_g3_io2 pb0 tsc_g3_io3 pb1 tsc_g3_io4 pb2 4 tsc_g4_io1 pa9 tsc_g4_io2 pa10 tsc_g4_io3 pa13 tsc_g4_io4 pa14 5 tsc_g5_io1 pb3 tsc_g5_io2 pb4 tsc_g5_io3 pb6 tsc_g5_io4 pb7 6 tsc_g6_io1 pb11 tsc_g6_io2 pb12 tsc_g6_io3 pb13 tsc_g6_io4 pb14 table 11. no. of capacitive se nsing channels available on stm32f301x6/8 devices analog i/o group number of capacitive sensing channels stm32f301rx stm32f301cx stm32f301kx g1 3 3 3 g2 3 3 3 g3 3 2 1 g4 3 3 3 g5 3 3 3 functional overview stm32f301x6 stm32f301x8 30/135 docid025146 rev 6 3.21 infrared transmitter the stm32f301x6/8 devices provide an infrared transmitter solution. the solution is based on internal connections between tim16 and tim17 as shown in the figure below. tim17 is used to provide the carrier frequenc y and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control sign als, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming t he two timers output compare channels. figure 3. infrared transmitter g6 3 3 0 number of capacitive sensing channels 18 17 13 table 11. no. of capacitive se nsing channels available on stm32f301x6/8 devices (continued) analog i/o group number of capacitive sensing channels stm32f301rx stm32f301cx stm32f301kx 7 , 0 ( 5 i r u h q y h o r s 7 , 0 ( 5 i r u f d u u l h u 2 & 2 & 3 % 3 $ 0 6 9 docid025146 rev 6 31/135 stm32f301x6 stm32f301x8 functional overview 51 3.22 development support 3.22.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. pinouts and pin description stm32f301x6 stm32f301x8 32/135 docid025146 rev 6 4 pinouts and pin description figure 4. stm32f301x6/8 ufqfn32 pinout 1. the above figure shows the package top view. figure 5. stm32f301x6/8 lqfp48 pinout 1. the above figure shows the package top view. 8 ) 4 ) 1 0 6 9 9 ' ' b 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 9 5 ( ) 9 6 6 $ 9 5 ( ) 3 $ 3 $ 9 6 6 b % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' b 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 9 6 6 b 3 $ 3 % 3 % 9 6 6 b % 2 2 7 3 % 3 % 3 % 9 ' ' b 9 6 6 b 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 b 3 % 9 ' ' b 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' b 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 0 6 9 / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ docid025146 rev 6 33/135 stm32f301x6 stm32f301x8 pinouts and pin description 51 figure 6. stm32f301x6/8 lqfp64 pinout 1. the above figure shows the package top view. 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' b 3 ' 3 & 3 & 3 & 9 ' ' b 9 6 6 b 3 & 3 & 3 & 3 % 9 6 6 b 3 $ 9 ' ' b 3 & 3 & 3 % 3 % 3 ) 2 6 & b 2 8 7 3 ) 2 6 & b , 1 3 & 9 6 6 b 3 % 9 6 6 b 9 ' ' b , 1 & 0 d l 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ pinouts and pin description stm32f301x6 stm32f301x8 34/135 docid025146 rev 6 figure 7. stm32f301x6/8 wlcsp49 ballout 1. the above figure shows the package top view. 2. nc: not connected. 0 6 9 $ % ( ' & ) * 3 & 9 ' ' 1 5 6 7 9 6 6 3 $ 9 ' ' $ 9 % $ 7 3 & 9 6 6 $ 9 5 ( ) 3 $ 3 $ % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 3 $ 9 6 6 3 $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 3 % 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 $ 3 % 3 ) 2 6 & b 2 8 7 3 ) 2 6 & b , 1 1 & docid025146 rev 6 35/135 stm32f301x6 stm32f301x8 pinouts and pin description 51 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, i2c fm+ option tta 3.3 v tolerant i/o tt 3.3 v tolerant i/o tc standard 3.3v i/o b dedicated boot0 pin rst bi-directional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected thro ugh gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers pinouts and pin description stm32f301x6 stm32f301x8 36/135 docid025146 rev 6 table 13. stm32f301x6/8 pin definitions pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 - b6 1 1 vbat s - - backup power supply -d52 2 pc13 (1) tamper1 wkup2 (pc13) i/o tc (1) tim1_ch1n wkup2, rtc_tamp1, rtc_ts, rtc_out -c73 3 pc14 (1) osc32_in (pc14) i/o tc (1) - osc32_in -c64 4 pc15 (1) osc32_out (pc14) i/o tc (1) - osc32_out 2 d7 5 5 pf0 osc_in (pf0) i/o ftf - i2c2_sda, spi2_nss/i2s2_ws, tim1_ch3n osc_in 3 d6 6 6 pf1 osc_out (pf1) o ftf - i2c2_scl, spi2_sck/i2s2_ck osc_out 4 e7 7 7 nrst i/o rst - device reset input/ internal reset output (active low) - - - 8 pc0 i/o tta - eventout, tim1_ch1 adc1_in6 - - - 9 pc1 i/o tta - eventout, tim1_ch2 adc1_in7 - - - 10 pc2 i/o tta - eventout, tim1_ch3 adc1_in8 ---11 pc3 i/o tta - eventout, tim1_ch4, tim1_bkin2 adc1_in9 6 e6 8 12 vssa/vref- s - - analog ground/negative reference voltage 5 a6 9 13 vdda/vref+ s - - analog power supply/positive reference voltage stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 37/135 7 f6 10 14 pa0 -tamper2-wkup1 i/o tta (2) tim2_ch1/tim2_etr, tsc_g1_io1, usart2_cts, eventout adc1_in1, rtc_tamp2, wkup1 8g71115 pa1 i/o tta (2) rtc_refin, tim2_ch2, tsc_g1_io2, usart2_rts_de, tim15_ch1n, eventout adc1_in2 9e51216 pa2 i/o tta (2) tim2_ch3, tsc_g1_io3, usart2_tx, comp2_out, tim15_ch1, eventout adc1_in3, comp2_inm 10 e4 13 17 pa3 i/o tta (2) tim2_ch4, tsc_g1_io4, usart2_rx, tim15_ch2, eventout adc1_in4 - f7 - 18 vss_4 s - - - - -f2-19 vdd_4 s - - - - 11 g6 14 20 pa4 i/o tta (2)(3) tsc_g2_io1, spi3_ nss/i2s3_ws, usart2_ck, eventout adc1_in5, dac1_out1, comp2_inm, comp4_inm, comp6_inm 12 f5 15 21 pa5 i/o tta - tim2_ch1/tim2_etr, tsc_g2_io2, eventout opamp2_vinm 13 f4 16 22 pa6 i/o tta (3) tim16_ch1, tsc_g2_io3, tim1_bkin, eventout adc1_in10, opamp2_vout 14 f3 17 23 pa7 i/o tta - tim17_ch1, tsc_g2_io4, tim1_ch1n, eventout adc1_in15, comp2_inp, opamp2_vinp table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6 stm32f301x8 38/135 docid025146 rev 6 ---24 pc4 i/o tt - eventout, tim1_etr, usart1_tx ---25 pc5 i/o tta - eventout, tim15_bkin, tsc_g3_io1, usart1_rx opamp2_vinm 15 g5 18 26 pb0 i/o tta - tsc_g3_io2, tim1_ch2n, eventout adc1_in11, comp4_inp, opamp2_vinp - g4 19 27 pb1 i/o tta - tsc_g3_io3, tim1_ch3n, comp4_out, eventout adc1_in12 - g3 20 28 pb2 i/o tta - tsc_g 3_io4, eventout comp4_inm - e3 21 29 pb10 i/o tt - tim2_ch3, tsc_sync, usart3_tx, eventout - g2 22 30 pb11 i/o tta - tim2_ch4, tsc_g6_io1, usart3_rx, eventout adc1_in14, comp6_inp 16 d3 23 31 vss_2 s - - digital ground 17 b2 24 32 vdd_2 s - - digital power supply - e2 25 33 pb12 i/o tt - tsc_g6_io2, i2c2_smbal, spi2_nss/i2s2_ws, tim1_bkin, usart3_ck, eventout - g1 26 34 pb13 i/o tta - tsc_g6_io3, spi2_ sck/i2s2_ck, tim1_ch1n, usart3_cts, eventout adc1_in13 table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 39/135 - f1 27 35 pb14 i/o tta - tim15_ch1, tsc_g6_io4, spi2_miso/i2s2ext_sd, tim1_ch2n, usart3_rts_de, eventout opamp2_vinp - e1 28 36 pb15 i/o tta - rtc_refin, tim15_ch2, tim15_ch1n, tim1_ch3n, spi2_mosi/i2s2_sd, eventout comp6_inm ---37 pc6 i/o ft - eventout, i2s2_mck, comp6_out - - - - 38 pc7 i/o ft - eventout, i2s3_mck - - - - 39 pc8 i/o ft - eventout - - - - 40 pc9 i/o ftf - eventout, i2c3_sda, i2sckin - 18 d1 29 41 pa8 i/o ft - mco, i2c3_scl, i2c2_smbal, i2s2_mck, tim1_ch1, usart1_ck, eventout - 19 d2 30 42 pa9 i/o ftf - i2c3_smbal, tsc_g4_io1, i2c2_scl, i2s3_mck, tim1_ch2, usart1_tx, tim15_bkin, tim2_ch3, eventout - table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6 stm32f301x8 40/135 docid025146 rev 6 20 c2 31 43 pa10 i/o ftf - tim17_bkin, tsc_g4_io2, i2c2_sda, spi2_miso/i2s2ext_sd, tim1_ch3, usart1_rx, comp6_out, tim2_ch4, eventout - 21 c1 32 44 pa11 i/o ft - spi2_mosi/i2s2_sd, tim1_ch1n, usart1_cts, tim1_ch4, tim1_bkin2, eventout 22 c3 33 45 pa12 i/o ft - tim16_ch1, i2sckin, tim1_ch2n, usart1_rts_de, comp2_out, tim1_etr, eventout 23 b3 34 46 pa13 i/o ft - swdio, tim16_ch1n, tsc_g4_io3, ir-out, usart3_cts, eventout - - b1 35 47 vss_3 s - - digital ground - b2 36 48 vdd_3 s - - digital power supply 24 a1 37 49 pa14 i/o ftf - swclk-jtck, tsc_g4_io4, i2c1_sda, tim1_bkin, usart2_tx, eventout - 25 a2 38 50 pa15 i/o ftf - jtdi, tim2_ch1/tim2_etr, tsc_sync, i2c1_scl, spi3_nss/i2s3_ws, usart2_rx, tim1_bkin, eventout - table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 41/135 ---51 pc10 i/o ft - eventout, spi3_sck/i2s3_ck, usart3_tx - ---52 pc11 i/o ft - eventout, spi3_miso/i2s3ext_sd, usart3_rx - ---53 pc12 i/o ft - eventout, spi3_mosi/i2s3_sd, usart3_ck - - - - 54 pd2 i/o ft - eventout - 26 a3 39 55 pb3 i/o ft - jtdo-traceswo, tim2_ch2, tsc_g5_io1, spi3_ sck/i2s3_ck, usart2_tx, eventout - 27 a4 40 56 pb4 i/o ft - jtrst, tim16_ch1, tsc_g5_io2, spi3_miso/i2s3ext_sd, usart2_rx, tim17_bkin, eventout - 28 b4 41 57 pb5 i/o ft - tim16_bkin, i2c1_smbal, spi3_mosi/i2s3_sd, usart2_ck, i2c3_sda, tim17_ch1, eventout - 29 c4 42 58 pb6 i/o ftf - tim16_ch1n, tsc_g5_io3, i2c1_scl, usart1_tx, eventout - 30 d4 43 59 pb7 i/o ftf - tim17_ch1n, tsc_g5_io4, i2c1_sda, usart1_rx, eventout - table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6 stm32f301x8 42/135 docid025146 rev 6 31 a5 44 60 boot0 i b - boot memory selection - b5 45 61 pb8 i/o ftf - tim16_ch1, tsc_sync, i2c1_scl, usart3_rx, tim1_bkin, eventout - - c5 46 62 pb9 i/o ftf - tim17_ch1, i2c1_sda, ir-out, usart3_tx, comp2_out, eventout - 32 d3 47 63 vss_1 s - - digital ground "1" b7 48 64 vdd_1 s - - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch sinks only a limited amount of current (3 ma), th e use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as curr ent sources (e.g. to drive an led). after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the main reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register description secti ons in the rm0366 reference manual. 2. fast adc channel. 3. these gpios offer a reduced t ouch sensing sensitivity. it is thus recommended to use them as sampling capacitor i/o. table 13. stm32f301x6/8 pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 43/135 table 14. alternate functions for port a port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 - - event pa0 - tim2 _ch1/ tim2 _etr - tsc _g1_io1 -- - usart2 _cts ------- event out pa1 rtc _refin tim2 _ch2 - tsc _g1_io2 -- - usart2 _rts_d e - tim15 _ch1n ----- event out pa2 - tim2 _ch3 - tsc _g1_io3 -- - usart2 _tx comp2 _out tim15 _ch1 ----- event out pa3 - tim2 _ch4 - tsc _g1_io4 -- - usart2 _rx - tim15 _ch2 ----- event out pa4 - - - tsc _g2_io1 -- spi3_nss/ i2s3_ws usart2 _ck ------- event out pa5 - tim2 _ch1/ tim2 _etr - tsc _g2_io2 - - - - ------- event out pa6 - tim16 _ch1 - tsc _g2_io3 - - tim1_bkin- ------- event out pa7 - tim17 _ch1 - tsc _g2_io4 -- tim1 _ch1n - ------- event out pa8 mco - - i2c3 _scl i2c2 _smbal i2s2 _mck tim1_ch1 usart1 _ck ------- event out pinouts and pin description stm32f301x6 stm32f301x8 44/135 docid025146 rev 6 pa9 - - i2c3 _smbal tsc _g4_io1 i2c2 _scl i2s3 _mck tim1_ch2 usart1 _tx - tim15 _bkin tim2 _ch3 ---- event out pa10 - tim17 _bkin tsc _g4_io2 i2c2 _sda spi2_mis o/i2s2ext _sd tim1_ch3 usart1 _rx comp6 _out - tim2 _ch4 ---- event out pa11----- spi2_mo si/i2s2 _sd tim1 _ch1n usart1 _cts --- tim1 _ch4 tim1 _bkin2 -- event out pa12 - tim16 _ch1 - - - i2sckin tim1 _ch2n usart1 _rts_d e comp2 _out -- tim1 _etr --- event out pa13 swdat- jtms tim16 _ch1n - tsc _g4_io3 -ir-out- usart3 _cts ------- event out pa14 swclk- jtck - tsc _g4_io4 i2c1 _sda - tim1_bkin usart2 _tx ------- event out pa15 jtdi tim2_c h1/ tim2_e tr - tsc _sync i2c1 _scl - spi3_nss/ i2s3_ws usart2 _rx - tim1 _bkin ----- event out table 14. alternate functions for port a (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 - - event stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 45/135 table 15. alternate functions for port b port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 - - event pb0 - - - tsc _g3_io2 -- tim1 _ch2n -------- event out pb1 - - - tsc _g3_io3 -- tim1 _ch3n - comp4_ out - - ---- event out pb2 tsc _g3_io4 ----------- event out pb3 jtdo- trace swo tim2 _ch2 - tsc _g5_io1 -- spi3_sc k/i2s3_ ck usart2 _tx ------- event out pb4 jtrst tim16 _ch1 - tsc _g5_io2 -- spi3_mi so/i2s3 _sd usart2 _rx -- tim17 _bkin ---- event out pb5 - tim16 _bkin -- i2c1 _smbal - spi3 _mosi/ i2s3ext_ sd usart2 _ck i2c3 _sda - tim17 _ch1 ---- event out pb6 - tim16 _ch1n - tsc _g5_io3 i2c1 _scl -- usart1 _tx ------- event out pb7 - tim17 _ch1n - tsc _g5_io4 i2c1 _sda -- usart1 _rx ------- event out pb8 - tim16 _ch1 - tsc _sync i2c1 _scl -- usart3 _rx ---- tim1 _bkin -- event out pinouts and pin description stm32f301x6 stm32f301x8 46/135 docid025146 rev 6 pb9 - tim17 _ch1 -- i2c1 _sda -ir-out usart3 _tx comp2_ out - - ---- event out pb10 - tim2 _ch3 - tsc _sync --- usart3 _tx ------- event out pb11 - tim2 _ch4 - tsc _g6_io1 --- usart3 _rx ------- event out pb12 - - - tsc _g6_io2 i2c2 _smbal spi2_ns s/i2s2_ ws tim1 _bkin usart3 _ck ------- event out pb13 - - - tsc _g6_io3 - spi2_sc k/ i2s2_ck tim1 _ch1n usart3 _cts ------- event out pb14 - tim15 _ch1 - tsc _g6_io4 - spi2_mi so/i2s2 ext_sd tim1 _ch2n usart3 _rts _de ------- event out pb15 rtc _refin tim15 _ch2 tim15 _ch1n - tim1 _ch3n spi2_m osi/ i2s2_sd --------- event out table 15. alternate functions for port b (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 - - event stm32f301x6 stm32f301x8 pinouts and pin description docid025146 rev 6 47/135 table 16. alternate functions for port c port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2 /tim15 i2c3/tim15/ tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3 infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/ usart2/ usart3/ gpcomp6 pc0 - eventout tim1_ch1 ----- pc1 - eventout tim1_ch2 ----- pc2 - eventout tim1_ch3 ----- pc3 - eventout tim1_ch4 --- tim1_bkin2 - pc4 - eventout tim1_etr ---- usart1_tx pc5 - eventout tim15_bkin tsc_g3_io1 --- usart1_rx pc6 - eventout ---- i2s2_mck comp6_out pc7 - eventout ---- i2s3_mck - pc8 - eventout ------ pc9 - eventout - i2c3_sda - i2sckin -- pc10 - eventout ---- spi3_sck/ i2s3_ck usart3_tx pc11 - eventout ---- spi3_miso/ i2s3ext_sd usart3_rx pc12 - eventout ---- spi3_mosi/ i2s3_sd usart3_ck pc13 ---- tim1_ch1n --- pc14 -------- pc15 -------- pinouts and pin description stm32f301x6 stm32f301x8 48/135 docid025146 rev 6 table 17. alternate functions for port d port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2/ tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/ infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/ usart2/ usart3/ gpcomp6 pd2 - eventout ------ table 18. alternate functions for port f port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2/ tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/ infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/usar t2/usart3/ gpcomp6 pf0 ---- i2c2_sda spi2_nss/ i2s2_ws tim1_ch3n - pf1 ---- i2c2_scl spi2_sck/ i2s2_ck -- docid025146 rev 6 49/135 stm32f301x6 stm32f301x8 memory mapping 51 5 memory mapping figure 8. stm32f301x6/8 memory mapping [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 s w l r q e \ w h v 6 \ v w h p p h p r u \ ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ [ [ [ ) ) [ [ & [ [ $ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) ' [ [ [ [ 5 h v h u y h g 0 6 y 9 $ + % [ ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g memory mapping stm32f301x6 stm32f301x8 50/135 docid025146 rev 6 table 19. stm32f301x6 stm32f301x8 peripheral register boundary addresses (1) bus boundary address size (bytes) peripheral ahb3 0x5000 0000 - 0x5000 03ff 1 k adc1 0x4800 1800 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k reserved 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0400 - 0x4002 0fff 3 k reserved 0x4002 0000 - 0x4002 03ff 1 k dma1 0x4001 8000 - 0x4001 ffff 32 k reserved apb2 0x4001 4c00 - 0x4001 7fff 13 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k reserved 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3000 - 0x4001 37ff 2 k reserved 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 8 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + opamp 0x4000 9c00 - 0x4000 ffff 25 k reserved docid025146 rev 6 51/135 stm32f301x6 stm32f301x8 memory mapping 51 apb1 0x4000 7c00 - 0x4000 9bff 8 k reserved 0x4000 7800 - 0x4000 7bff 1 k i2c3 0x4000 7400 - 0x4000 77ff 1 k dac1 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 5c00 - 0x4000 6fff 5 k reserved 0x4000 5800 - 0x4000 5bff 1 k i2c2 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 4c00 - 0x4000 53ff 2 k reserved 0x4000 4800 - 0x4000 4bff 1 k usart3 0x4000 4400 - 0x4000 47ff 1 k usart2 0x4000 4000 - 0x4000 43ff 1 k i2s3ext 0x4000 3c00 - 0x4000 3fff 1 k spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 k spi2/i2s2 0x4000 3400 - 0x4000 37ff 1 k i2s2ext 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k rtc 0x4000 1400 - 0x4000 27ff 5 k reserved 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0400 - 0x4000 0fff 3 k reserved 0x4000 0000 - 0x4000 03ff 1 k tim2 0x2000 4000 - 3fff ffff ~512 m reserved 0x2000 0000 - 0x2000 3fff 16 k sram 0x1fff f800 - 0x1fff ffff 2 k option bytes 0x1fff d800 - 0x1fff f7ff 8 k system memory 0x0801 0000 - 0x1fff d7ff ~384 m reserved 0x0800 0000 - 0x0800 ffff 64 k main flash memory 0x0001 0000 - 0x07ff ffff ~128 m reserved 0x0000 000 - 0x0000 ffff 64 k main flash memory, system memory or sram depending on boot configuration 1. the gray color is used for reserved flash memory addresses. table 19. stm32f301x6 stm32f301x8 peripheral register boundary addresses (continued) (1) bus boundary address size (bytes) peripheral electrical characteristics stm32f301x6 stm32f301x8 52/135 docid025146 rev 6 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 9. pin loading conditions figure 10. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid025146 rev 6 53/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.1.6 power supply scheme figure 11. power supply scheme caution: each power supply pair (for example v dd /v ss , v dda /v ssa ) must be decoupled with filtering ceramic capacitors as shown above. these capa citors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 9 / h y h o v k l i w h u $ q d o r j 5 & v 3 / / f r p s d u d w r u v 2 3 $ 0 3 3 r z h u v z l w f k $ ' & ' $ & . h u q h o o r j l f & 3 8 g l j l w d o p h p r u l h v , 2 o r j l f % d f n x s f l u f x l w u \ / 6 ( 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v 9 % $ 7 9 * 3 , 2 v 9 ' ' 2 8 7 , 1 5 h j x o d w r u [ 9 ' ' [ 9 6 6 9 ' ' $ 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ [ q ) [ ? ) q ) ? ) electrical characteristics stm32f301x6 stm32f301x8 54/135 docid025146 rev 6 6.1.7 current consumption measurement figure 12. current consum ption measurement scheme 0 6 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' , ' ' $ , ' ' b 9 % $ 7 docid025146 rev 6 55/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 20: voltage characteristics , table 21: current characteristics , and table 22: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 20. voltage characteristics (1) symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda, v bat and v dd ) -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4v v in (2) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 v input voltage on tta and tt pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on boot0 pin 0 9 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins (3) -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics v 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. the following relationship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . 2. v in maximum must always be respected. refer to table 21: current characteristics for the maximum allowed injected current values. 3. include v ref- pin. electrical characteristics stm32f301x6 stm32f301x8 56/135 docid025146 rev 6 table 21. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd_x power lines (source) 130 ma i vss total current out of sum of all vss_x ground lines (sink) -130 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin -25 i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on tt, ft, ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) +/-5 injected current on tta pins (5) +/-5 i inj(pin) total injected current (sum of all i/o and control pins) (6) +/-25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins.the total output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 20: voltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in > v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to table 20: voltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performance of the device. see note (2) below table 66 . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 22. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025146 rev 6 57/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3 operating conditions 6.3.1 general operating conditions table 23. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 72 mhz f pclk1 internal apb1 clock frequency - 0 36 f pclk2 internal apb2 clock frequency - 0 72 v dd standard operating voltage - 2 3.6 v v dda analog operating voltage (opamp and dac not used) must have a potential equal to or higher than v dd 23.6 v analog operating voltage (opamp and dac used) 2.4 3.6 v bat backup operating voltage - 1.65 3.6 v v in i/o input voltage tc i/o ?0.3 v dd +0.3 v tt i/o (1) -0.3 3.6 tta i/o pins ?0.3 v dda +0.3 ft and ftf i/o (1) 1. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. ?0.3 5.5 boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . see table 80: package thermal characteristics . lqfp64 - 444 mw lqfp48 - 364 wlcsp49 - 408 ufqfpn32 - 540 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (3) 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . see table 80: package thermal characteristics ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 electrical characteristics stm32f301x6 stm32f301x8 58/135 docid025146 rev 6 6.3.2 operating conditions at power-up / power-down the parameters given in table 24 are derived from tests performed under the ambient temperature condition summarized in table 23 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 25 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . table 24. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 25. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - - 40 - mv t rsttempo (3) 3. based on characterization, not tested in production. por reset temporization - 1.5 2.5 4.5 ms docid025146 rev 6 59/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 26. programmable voltage detector characteristics symbol parameter conditions min (1) 1. guaranteed by characterization results. typ max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 falling edge 2.09 2.18 2.27 v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 falling edge 2.18 2.28 2.38 v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 falling edge 2.28 2.38 2.48 v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 falling edge 2.37 2.48 2.59 v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 falling edge 2.47 2.58 2.69 v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 falling edge 2.56 2.68 2.8 v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 falling edge 2.66 2.78 2.9 v pvdhyst (2) 2. guaranteed by design. pvd hysteresis - - 100 - mv idd(pvd) pvd current consumption - - 0.15 0.26 a electrical characteristics stm32f301x6 stm32f301x8 60/135 docid025146 rev 6 6.3.4 embedded reference voltage the parameters given in table 27 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 12: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. note: the total current consumption is the sum of i dd and i dda . table 27. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.20 1.23 1.25 v t s_vrefint adc sampling time when reading the internal reference voltage -2.2--s v rerint internal reference voltage spread over the temperature range v dd = 3 v 10 mv - - 10 (1) 1. guaranteed by design. mv t coeff temperature coefficient - - - 100 (1) ppm/ c table 28. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb docid025146 rev 6 61/135 stm32f301x6 stm32f301x8 electrical characteristics 114 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 ? when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in table 29 to table 35 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 23 . table 29. typical and maximum current consumption from vdd supply at vdd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 45.7 48.6 50.0 52.0 25.5 27.5 28.1 28.8 ma 64 mhz 40.6 43.6 44.5 46.4 22.7 24.6 25.2 25.9 48 mhz 30.8 33.6 34.1 35.5 17.3 19.0 19.5 20.0 32 mhz 21.0 22.9 23.5 25.6 11.7 13.2 13.7 14.1 24 mhz 16.0 16.8 18.0 18.9 9.0 10.4 10.8 11.4 8 mhz 5.4 5.6 6.1 7.2 3.3 3.3 3.8 4.2 1 mhz 1.1 1.2 1.7 2.7 0.8 0.9 1.3 1.6 internal clock (hsi) 64 mhz 37.6 41.3 42.9 44.7 22.5 24.7 25.0 25.8 48 mhz 28.7 32.3 33.1 34.0 17.2 19.1 19.4 19.6 32 mhz 19.5 22.0 23.4 24.6 11.5 12.9 13.5 13.7 24 mhz 14.9 16.6 17.9 18.4 6.0 7.0 7.4 7.9 8 mhz 5.2 5.5 6.4 7.0 3.2 3.8 4.3 4.7 electrical characteristics stm32f301x6 stm32f301x8 62/135 docid025146 rev 6 i dd supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 45.8 49.1 (2) 50.1 51.4 (2) 25.1 27.3 (2) 28.0 28.6 (2) ma 64 mhz 40.8 43.6 44.9 46.9 22.3 24.1 25.0 25.5 48 mhz 30.2 32.9 33.5 34.8 17.0 18.7 19.1 19.6 32 mhz 20.5 23.1 24.1 25.4 11.1 12.2 13.2 13.3 24 mhz 15.4 17.1 18.3 19.5 8.5 9.7 10.1 10.2 8 mhz 5.0 5.9 6.3 6.9 3.1 3.7 4.1 4.7 1 mhz 0.8 1.1 1.9 2.6 0.5 0.8 1.2 1.4 internal clock (hsi) 64 mhz 37.3 41.1 41.8 43.3 22.0 23.8 24.4 24.9 48 mhz 28.0 31.1 31.6 33.2 16.4 18.0 18.3 18.6 32 mhz 18.8 21.3 22.1 23.1 10.9 11.9 12.8 13.1 24 mhz 14.2 15.9 16.8 17.9 5.5 6.4 6.7 7.3 8 mhz 4.8 5.1 6.0 6.5 2.9 3.5 4.1 4.2 i dd supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 30.0 32.8 (2) 33.1 34.1 (2) 5.9 6.8 (2) 6.9 7.4 (2) 64 mhz 26.7 29.2 29.6 30.5 5.3 5.9 6.2 6.7 48 mhz 16.7 18.5 19.0 19.7 3.6 4.5 4.5 5.3 32 mhz 13.3 14.9 15.3 15.4 2.9 3.7 3.8 4.3 24 mhz 10.2 11.4 12.0 12.3 2.2 2.7 2.9 3.2 8 mhz 3.6 4.4 4.8 5.3 0.9 1.2 1.5 2.1 1 mhz 0.5 0.8 1.1 1.3 0.1 0.4 0.8 0.8 internal clock (hsi) 64 mhz 23.2 25.3 25.6 26.2 5.0 5.7 6.1 6.2 ma 48 mhz 17.5 19.2 19.4 19.9 3.9 4.7 4.8 5.3 32 mhz 11.7 12.9 13.2 13.3 2.6 3.4 3.6 4.2 24 mhz 8.9 10.2 10.6 10.8 1.4 2.1 2.4 2.7 8 mhz 3.4 4.0 4.6 5.1 0.7 1.1 1.4 1.9 1. guaranteed by characterization results. 2. data based on characterization results and test ed in production with code executing from ram. table 29. typical and maximum current consumption from vdd supply at vdd = 3.6v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c docid025146 rev 6 63/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 30. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run/sleep mode, code executing from flash or ram hse bypass 72 mhz 231 254 (3) 266 271 (3) 251 274 (3) 294 300 (3) a 64 mhz 203 226 239 243 222 245 261 266 48 mhz 153 174 182 186 165 185 198 203 32 mhz 105 124 131 133 114 132 141 143 24 mhz 82 98 104 105 89 106 111 113 8 mhz 3.1 4.1 4.1 5.1 3.6 4.7 5.2 5.5 1 mhz 3.1 4.1 4.1 5.1 3.6 4.7 5.2 5.5 hsi clock 64 mhz 270 294 307 312 296 322 338 343 48 mhz 219 242 253 257 240 263 276 281 32 mhz 171 192 201 203 188 209 219 222 24 mhz 148 169 175 177 163 182 190 193 8 mhz 69 84 87 87 79 92 94 96 1. current consumption from the v dda supply is independent of whether the peripherals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. guaranteed by characterization results. 3. data based on characterization results and tested in production. table 31. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd =v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 16.92 17.09 17.16 17.27 17.39 17.50 29.7 359.1 564.5 a regulator in low-power mode, all oscillators off 5.29 5.46 5.55 5.70 5.73 5.95 16.40 267.1 407.4 supply current in standby mode lsi on and iwdg on 0.80 0.93 1.11 1.19 1.31 1.41 - - - lsi off and iwdg off 0.63 0.76 0.84 0.95 1.02 1.10 5.00 6.30 12.60 1. guaranteed by characterization results. electrical characteristics stm32f301x6 stm32f301x8 64/135 docid025146 rev 6 table 32. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda supervisor on regulator in run/low- power mode, all oscillators off 1.70 1.83 1.95 2.08 2. 22 2.37 3.40 5.30 5.5 a supply current in standby mode lsi on and iwdg on 2.08 2.25 2.41 2.59 2.79 3.01 - - - lsi off and iwdg off 1.59 1.72 1.83 1.96 2. 10 2.25 2.80 2.90 3.60 supply current in stop mode v dda supervisor off regulator in run/low- power mode, all oscillators off 0.99 1.01 1.04 1.09 1.14 1.21 - - - supply current in standby mode lsi on and iwdg on 1.36 1.43 1.50 1.60 1.72 1.85 - - - lsi off and iwdg off 0.87 0.89 0.92 0.97 1.02 1.09 - - - 1. guaranteed by characterization results. table 33. typical and maximum current consumption from v bat supply symbol para meter conditions (1) typ.@v bat max. @v bat = 3.6v (2) t a (c) unit 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v 25 85 105 i dd_vbat backup domain supply current lse & rtc on; ?xtal mode? lower driving capability; lsedrv[1: 0] = '00' 0.41 0.43 0.46 0.54 0.59 0.66 0.74 0.82 - - - a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1: 0] = '11' 0.65 0.68 0.73 0.80 0.87 0.95 1.03 1.14 - - - 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. guaranteed by characterization results. docid025146 rev 6 65/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins available on each packag e are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on ? when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. 0 6 0 6 [ [ [ [ [ 9 \ ? & ? & ? & ? & ? $ , 9 % $ 7 7 $ ? & 9 9 9 9 9 9 9 9 electrical characteristics stm32f301x6 stm32f301x8 66/135 docid025146 rev 6 table 34. typical current consumption in run m ode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 44.8 24.9 ma 64 mhz 40.0 22.4 48 mhz 30.3 17.1 32 mhz 20.7 11.9 24 mhz 15.8 9.2 16 mhz 10.9 6.5 8 mhz 5.7 3.55 4 mhz 3.43 3.22 2 mhz 2.18 1.53 1 mhz 1.56 1.19 500 khz 1.25 0.96 125 khz 0.96 0.84 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 237.1 a 64 mhz 208.3 48 mhz 154.3 32 mhz 105.0 24 mhz 81.3 16 mhz 57.8 8 mhz 1.15 4 mhz 1.15 2 mhz 1.15 1 mhz 1.15 500 khz 1.15 125 khz 1.15 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. docid025146 rev 6 67/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 35. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 28.7 6.1 ma 64 mhz 25.6 5.5 48 mhz 19.3 4.26 32 mhz 13.1 3.04 24 mhz 10.0 2.42 16 mhz 6.8 1.81 8 mhz 3.54 0.98 4 mhz 2.35 0.88 2 mhz 1.64 0.80 1 mhz 1.28 0.77 500 khz 1.11 0.75 125 khz 0.92 0.74 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 237.1 a 64 mhz 208.3 48 mhz 154.3 32 mhz 105.0 24 mhz 81.3 16 mhz 57.8 8 mhz 1.15 4 mhz 1.15 2 mhz 1.15 1 mhz 1.15 500 khz 1.15 125 khz 1.15 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. electrical characteristics stm32f301x6 stm32f301x8 68/135 docid025146 rev 6 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 54: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 37: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext +c s the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = docid025146 rev 6 69/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 36. switching output i/o current consumption symbol parameter conditions (1) i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.90 ma 4 mhz 0.93 8 mhz 1.16 18 mhz 1.60 36 mhz 2.51 48 mhz 2.97 v dd = 3.3 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.93 4 mhz 1.06 8 mhz 1.47 18 mhz 2.26 36 mhz 3.39 48 mhz 5.99 v dd = 3.3 v c ext = 22 pf c = c int + c ext +c s 2 mhz 1.03 4 mhz 1.30 8 mhz 1.79 18 mhz 3.01 36 mhz 5.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.10 4 mhz 1.31 8 mhz 2.06 18 mhz 3.47 36 mhz 8.35 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.20 4 mhz 1.54 8 mhz 2.46 18 mhz 4.51 1. cs = 5 pf (estimated value). electrical characteristics stm32f301x6 stm32f301x8 70/135 docid025146 rev 6 on-chip peripheral current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input configuration ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature at 25c and v dd = v dda = 3.3 v. docid025146 rev 6 71/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 37. peripheral current consumption peripheral typical consumption (1) unit i dd busmatrix (2) 11.3 a/mhz dma1 6.7 crc 2.0 gpioa 8.5 gpiob 8.3 gpioc 8.6 gpiod 1.5 gpiof 1.0 tsc 4.7 adc1 15.9 apb2-bridge (3) 2.7 syscfg 3.2 tim1 27.6 usart1 21.0 tim15 14.3 tim16 10.1 tim17 10.4 apb1-bridge (3) 5.8 tim2 40.7 tim6 7.4 wwdg 4.6 spi2 35.2 spi3 34.2 usart2 13.9 usart3 13.1 i2c1 9.4 i2c2 9.4 pwr 4.5 dac 8.3 i2c3 10.5 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of char acteristics in the subsequent sections. 2. busmatrix is automatically active when at least one master is on (cpu or dma1). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. electrical characteristics stm32f301x6 stm32f301x8 72/135 docid025146 rev 6 6.3.6 wakeup time from low-power mode the wakeup times given in table 38 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep mode: the wakeup event is wfe. ? wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . table 38. low-power mode wakeup timings symbol parameter conditions typ @v dd, v dd = v dda max unit 2.0 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v t wustop wakeup from stop mode regulator in run mode 4.5 4.2 4.1 4.0 3.8 3.8 4.5 s regulator in low-power mode 8.2 7.0 6.4 6.0 5.7 5.5 9.0 t wustandby (1) wakeup from standby mode lsi and iwdg off 72.8 63.4 59.2 56.1 53.1 51.3 103 t wusleep wakeup from sleep mode -6- cpu clock cycles 1. guaranteed by characterization results. table 39. wakeup time using usart (1) symbol parameter conditions typ max unit t wuusart wakeup time needed to calculate the maximum usart baud rate allowing to wakeup up from stop mode when the usart clock source is hsi stop mode with main regulator in low-power mode - 13.125 s stop mode with main regulator in run mode - 3.125 1. guaranteed by design. docid025146 rev 6 73/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 14 . figure 14. high-speed external clock source ac timing diagram table 40. high-speed external user clock characteristics symbol parameter condi tions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design. - 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / electrical characteristics stm32f301x6 stm32f301x8 74/135 docid025146 rev 6 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 15 figure 15. low-speed external clock source ac timing diagram table 41. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design. - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / docid025146 rev 6 75/135 stm32f301x6 stm32f301x8 electrical characteristics 114 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 42 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). table 42. hse oscilla tor characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) 2. guaranteed by design. typ max (2) unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 - k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time. --8.5 ma v dd =3.3 v, rm= 30 , cl=10 pf@8 mhz -0.4- v dd =3.3 v, rm= 45 , cl=10 pf@8 mhz -0.5- v dd =3.3 v, rm= 30 , cl= 5 pf@32 mhz -0.8- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -1- v dd =3.3 v, rm= 30 , cl=20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms electrical characteristics stm32f301x6 stm32f301x8 76/135 docid025146 rev 6 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 16. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid025146 rev 6 77/135 stm32f301x6 stm32f301x8 electrical characteristics 114 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 43 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 43. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]=10 medium low driving capability --1 lsedrv[1:0]=01 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]=10 medium low driving capability 8- - lsedrv[1:0]=01 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design. 3. t su(lse) is the startup time measured from the moment it is ena bled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. electrical characteristics stm32f301x6 stm32f301x8 78/135 docid025146 rev 6 figure 17. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid025146 rev 6 79/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.8 internal clock source characteristics the parameters given in table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 23 . high-speed internal (hsi) rc oscillator figure 18. hsi oscillator accuracy characterization results for soldered parts table 44. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design. % ducy (hsi) duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator t a = -40 to 105c -2.8 (3) 3. guaranteed by characterization results. -3.8 (3) % t a = -10 to 85c -1.9 (3) -2.3 (3) t a = 0 to 85c -1.9 (3) -2 (3) t a = 0 to 70c -1.3 (3) -2 (3) t a = 0 to 55c -1 (3) -2 (3) t a = 25c (4) 4. factory calibrated, parts not soldered. -1 - 1 t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - - 80 100 (2) a 0 6 9 5 < ? $ > " . " 9 . * / electrical characteristics stm32f301x6 stm32f301x8 80/135 docid025146 rev 6 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 23 . table 45. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 46. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -72mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design. ps docid025146 rev 6 81/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 47. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 48. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization results. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 electrical characteristics stm32f301x6 stm32f301x8 82/135 docid025146 rev 6 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 49 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 49. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-4 4a docid025146 rev 6 83/135 stm32f301x6 stm32f301x8 electrical characteristics 114 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 50. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp64 package compliant with iec 61967-2 0.1 to 30 mhz 5 dbv 30 to 130 mhz 6 130 mhz to 1ghz 28 sae emi level 4 - table 51. esd absolute maximum ratings symbol ratings conditions packages class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 all 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 lqfp64, wlcsp49 c3 250 v all other c4 500 1. guaranteed by characterization results. electrical characteristics stm32f301x6 stm32f301x8 84/135 docid025146 rev 6 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the test results are given in table 53 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 52. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a 2 level a table 53. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on pc0 pin (tta pin) -0 +5 injected current pc0, pc1, pc 2, pc3, pa0, pa1, pa2, pa3, pa4, pa6, pa7, pc4, pb0, pb10, pb11, pb13 with induced leakage current on other pins from this group less than -100 a or more than +100 a -5 +5 injected current on any other tt, ft and ftf pins -5 na injected current on all other tc, tta and reset pins -5 +5 docid025146 rev 6 85/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 54 are derived from tests performed under the conditions summarized in table 23 . all i/os are cmos and ttl compliant. table 54. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tta and tt i/o - - 0.3 v dd + 0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 i/o - - 0.3 v dd ? 0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tta and tt i/o 0.445 v dd +0.398 (1) -- v ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft and ftf i/o tta i/o in digital mode v ss v in v dd --0.1 a tta i/o in digital mode v dd v in v dda --1 tta i/o in analog mode v ss v in v dda --0.2 ft and ftf i/o (4) v dd v in 5 v --10 r pu weak pull-up equivalent resistor (5) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (5) v in = v dd 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation 2. tested in production. 3. leakage could be higher than the maximum value. if n egative current is injected on adjacent pins. refer to table 53: i/o current injection susceptibility . 4. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. 5. pull-up and pull-down resistors are designed with a true re sistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). electrical characteristics stm32f301x6 stm32f301x8 86/135 docid025146 rev 6 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 19 and figure 20 for standard i/os. figure 19. tc and tta i/o input characteristics - cmos port figure 20. tc and tta i/o input characteristics - ttl port figure 21. five volt tole rant (ft and ftf) i/o input characteristics - cmos port 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 9 ' ' 9 9 , / 9 , + 9 $ u h d q r w g h w h u p l q h g - 3 6 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' docid025146 rev 6 87/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 22. five volt tolerant (ft and ftf) i/o input characteristics - ttl port 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p l q 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v electrical characteristics stm32f301x6 stm32f301x8 88/135 docid025146 rev 6 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 21 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 21 ). output voltage levels unless otherwise specified, the parameters given in table 55 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. table 55. output voltage characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 21 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 21 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 4. data based on design simulation. docid025146 rev 6 89/135 stm32f301x6 stm32f301x8 electrical characteristics 114 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 23 and table 56 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 23 . table 56. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v - 125 (3) ns t r(io)out output low to high level rise time - 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 (3) mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 (3) mhz c l = 50 pf, v dd = 2 v to 2.7 v - 20 (3) mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v -2 (4) mhz t f(io)out output high to low level fall time -12 (4) ns t r(io)out output low to high level rise time -34 (4) -t extipw pulse width of external signals detected by the exti controller -10-?ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the rm0366 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 23 . 3. guaranteed by design. 4. the i/o speed configuration is bypassed in fm+ i/o m ode. refer to the stm32f301x6 stm32f301x8 reference manual rm0366 for a description of fm+ i/o mode configuration. electrical characteristics stm32f301x6 stm32f301x8 90/135 docid025146 rev 6 figure 23. i/o ac charac teristics definition 1. see table 56: i/o ac characteristics . 6.3.15 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 54 ). unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . 0 6 9 w u , 2 r x w ( [ w h u q d o r x w s x w r q & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / 7 w i , 2 r x w v h h q r w h table 57. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage - 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - - 200 - mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) (1) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) (1) nrst input not filtered pulse - 500 (1) --ns 1. guaranteed by design. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . docid025146 rev 6 91/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 24. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 57 . otherwise the reset will not be taken into account by the device. 3. the user must place the external capacito r on nrst as close as possible to the chip. 6.3.16 timer characteristics the parameters given in table 58 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 0 6 9 5 3 8 9 ' ' , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 58. timx (1)(2) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim15, tim16 and tim17 timers. 2. guaranteed by design. symbol parameter conditions min max unit t res(tim) timer resolution time -1- t timxclk f timxclk = 72 mhz 13.9 - ns f timxclk = 144 mhz, x = 1, 15,16, 17 6.95 - ns f ext timer external clock frequency on ch1 to ch4 -0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s f timxclk = 144 mhz, x= 1/15/16/17 0.0069 455 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 72 mhz - 59.65 s f timxclk = 144 mhz, x= 1/15/16/17 - 29.825 s electrical characteristics stm32f301x6 stm32f301x8 92/135 docid025146 rev 6 table 59. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller inter nal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout (ms) rl[11:0]= 0x000 max timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 60. wwdg min-max timeout value @72 mhz (pclk) (1) 1. guaranteed by design. prescaler wdgtb min timeout value max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 docid025146 rev 6 93/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.17 communications interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos connected between the i/o pin and vddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 61. i2c analog filter characteristics (1) 1. guaranteed by design. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns electrical characteristics stm32f301x6 stm32f301x8 94/135 docid025146 rev 6 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 62 for spi or in table 63 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 23 . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (n ss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 62. spi characteristics (1) 1. guaranteed by characterization results. symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode - - 18 mhz slave mode - - 18 t su(nss) nss setup time slave mode, spi presc = 2 4*tpcl k -- ns t h(nss) nss hold time slave mode, spi presc = 2 2*tpcl k -- t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk- 2 tpclk tpclk+ 2 t su(mi) t su(si) data input setup time master mode 0 - - slave mode 1 - - t h(mi) data input hold time master mode 6.5 - - t h(si) slave mode 2.5 - - t a(so) data output access time slave mode 8 - 40 t dis(so) data output disable time slave mode 8 - 14 t v(so) data output valid time slave mode - 12 27 t v(mo) master mode - 1.5 4 t h(so) data output hold time slave mode 7.5 - - t h(mo) master mode 0 - - docid025146 rev 6 95/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 25. spi timing diagram - slave mode and cpha = 0 figure 26. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 electrical characteristics stm32f301x6 stm32f301x8 96/135 docid025146 rev 6 figure 27. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 table 63. i2s characteristics (1) symbol parameter cond itions min max unit f mck i2s main clock output - 256 x 8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % docid025146 rev 6 97/135 stm32f301x6 stm32f301x8 electrical characteristics 114 note: refer to rm0366 reference manual i2s section for more details about the sampling frequency (fs), fmck, fc k, dck values reflect only the di gital peripheral behavior, source clock precision might slightly change the va lues dck depends main ly on odd bit value. digital contribution leads to a min of (i2sdiv/(2*i2sdi v+odd) and a max (i2sdiv+odd)/(2*i2sdiv+odd) and fs max supported for each mode/condition. t v(ws) ws valid time master mode - 20 ns t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 0 - t h(ws) ws hold time slave mode 4 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 1 - t h(sd_mr) data input hold time master receiver 8 - t h(sd_sr) slave receiver 2.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 50 t v(sd_mt) master transmitter (after enable edge) -22 t h(sd_st) data output hold time slave transmitter (after enable edge) 8 - t h(sd_mt) master transmitter (after enable edge) 1- 1. guaranteed by characterization results. 2. 256xfs maximum is 36 mhz (apb1 maximum frequency) table 63. i2s characteristics (1) (continued) symbol parameter cond itions min max unit electrical characteristics stm32f301x6 stm32f301x8 98/135 docid025146 rev 6 figure 28. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 29. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t stm32f301x6 stm32f301x8 electrical characteristics docid025146 rev 6 99/135 6.3.18 adc characteristics unless otherwise specified, the parameters given in table 64 to table 66 are guaranteed by design, with conditions summarized in table 23 . table 64. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc -2-3.6v i dda adc current consumption (see figure 30 ) single-ended mode, 5 msps - 1011.3 1172.0 a single-ended mode, 1 msps - 214.7 322.3 single-ended mode, 200 ksps - 54.7 81.1 differential mode, 5 msps - 1061.5 1243.6 differential mode, 1 msps - 246.6 337.6 differential mode, 200 ksps - 56.4 83.0 f adc adc clock frequency - 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits - - 5.14 mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range - 0 - v dda v r ain (1) external input impedance - - - 100 k electrical characteristics stm32f301x6 stm32f301x8 100/135 docid025146 rev 6 c adc (1) internal sample and hold capacitor --5-pf t cal (1) calibration time f adc = 72 mhz 1.56 s -1121/f adc t latr (1) trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 11 - - 2.125 1/f adc t latrinj (1) trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 11 - - 3.125 1/f adc t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s -1.5-601.51/f adc tadcvreg_stup (1) adc voltage regulator start-up time ---10s t stab (1) power-up time - 1 conversion cycle t conv (1) total conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 8.52 s resolution = 12 bits 14 to 614 (t s for sampling + 12.5 for successive approximation) 1/f adc cmir (1) common mode input signal adc differential mode (v ssa + v ref+ )/2 - 0.18 (v ssa + v ref+ )/2 (v ssa + v ref+ )/2 + 0.18 v 1. data guaranteed by design. table 64. adc characteristics (continued) symbol parameter conditions min typ max unit docid025146 rev 6 101/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 30 illustrates the adc current consumption as per the clock frequency in single- ended and differential modes. figure 30. adc typical current consumption in single-ended and differential modes 0 6 9 $ ' & f x u u h q w f r q v x p s w l r q ? $ & o r f n i u h t x h q f \ 0 6 3 6 table 65. maximum adc r ain (1) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (2) slow channels other channels (3) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 electrical characteristics stm32f301x6 stm32f301x8 102/135 docid025146 rev 6 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. guaranteed by characterization results. 2. all fast channels, expect channel on pa6. 3. channel available on pa6. table 65. maximum adc r ain (1) (continued) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (2) slow channels other channels (3) docid025146 rev 6 103/135 stm32f301x6 stm32f301x8 electrical characteristics 114 table 66. adc accuracy - limited test conditions (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. 72 mhz sampling freq. 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms - 4 4.5 lsb slow channel 4.8 ms - 5.5 6 differential fast channel 5.1 ms - 3.5 4 slow channel 4.8 ms - 3.5 4 eo offset error single ended fast channel 5.1 ms - 2 2 slow channel 4.8 ms - 1.5 2 differential fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 2 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 5 5.5 differential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3.5 ed differential linearity error single ended fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 2 3 differential fast channel 5.1 ms - 1.5 1.5 slow channel 4.8 ms - 1.5 2 enob (4) effective number of bits single ended fast channel 5.1 ms 10.8 10.8 - bit slow channel 4.8 ms 10.8 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.2 11.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - electrical characteristics stm32f301x6 stm32f301x8 104/135 docid025146 rev 6 snr (4) signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) to ta l harmonic distortion single ended fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -78 -77 differential fast channel 5.1 ms - -83 -82 slow channel 4.8 ms - -81 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. guaranteed by characterization results. 4. value measured with a ?0.5db full scale 50khz sine wave input signal. table 66. adc accuracy - limited test conditions (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit docid025146 rev 6 105/135 stm32f301x6 stm32f301x8 electrical characteristics 114 l table 67. adc accuracy (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 2.0 v v dda 3.6 v single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4.5 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2.5 slow channel 4.8 ms - 2.5 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3.5 slow channel 4.8 ms - 4 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3.5 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2.5 enob (5) effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.4 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - sinad (5) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - electrical characteristics stm32f301x6 stm32f301x8 106/135 docid025146 rev 6 snr (5) signal-to- noise ratio adc clock freq. 72 mhz, sampling freq 5 msps, 2 v v dda 3.6 v single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd (5) to ta l harmonic distortion single ended fast channel 5.1 ms - -75 slow channel 4.8 ms - -75 differential fast channel 5.1 ms - -79 slow channel 4.8 ms - -78 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. guaranteed by characterization results. 5. value measured with a ?0.5db full scale 50khz sine wave input signal. table 67. adc accuracy (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit table 68. adc accuracy (1)(2) symbol parameter test conditions typ max (3) unit et total unadjusted error adc freq 72 mhz sampling freq 1msps 2.4 v v dda = v ref+ 3.6 v single-ended mode fast channel 2.5 5 lsb slow channel 3.5 5 eo offset error fast channel 1 2.5 slow channel 1.5 2.5 eg gain error fast channel 2 3 slow channel 3 4 ed differential linearity error fast channel 0.7 2 slow channel 0.7 2 el integral linearity error fast channel 1 3 slow channel 1.2 3 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any analog input pi ns should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentia lly inject negative current. any positive injection current within the limits specified for iinj(pin) and iinj(pin) in section 6.3.14: i/o port characteristics does not affect the adc accuracy. 3. guaranteed by characterization results. docid025146 rev 6 107/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 31. adc accuracy characteristics figure 32. typical connecti on diagram using the adc 1. refer to table 64 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 11 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o 8 q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ 9 ' ' $ / 6 % , ' ( $ / 0 6 9 e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u 5 $ , 1 $ , 1 [ 9 $ , 1 & s d u d v l w l f 9 ' ' 9 7 9 9 7 9 , / ? ? $ 5 $ ' & & $ ' & 0 6 9 electrical characteristics stm32f301x6 stm32f301x8 108/135 docid025146 rev 6 6.3.19 dac electri cal specifications table 69. dac characteristics symbol parameter conditions min typ max unit v dda analog supply voltage dac output buffer on 2.4 - 3.6 v r load (1) resistive load dac output buffer on connected to v ssa 5- - k connected to v dda 25 - - r o (1) output impedance dac output buffer on - - 15 k c load (1) capacitive load dac output buffer on - - 50 pf v dac_out (1) voltage on dac_out output corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac output buffer on. 0.2 - v dda ? 0.2 v dac output buffer off - 0.5 v dda - 1lsb mv i dda (3) dac dc current consumption in quiescent mode (standby mode) (2) with no load, middle code (0x800) on the input. -- 380a with no load, worst code (0xf1c) on the input. - - 480 a dnl (3) differential non linearity difference between two consecutive code- 1lsb) given for a 10-bit input code - - 0.5 lsb given for a 12-bit input code - - 2 lsb inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095) given for a 10-bit input code - - 1 lsb given for a 12-bit input code - - 4 lsb offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) ---10mv given for a 10-bit input code at v dda = 3.6 v - - 3 lsb given for a 12-bit input code at v dda = 3.6 v - - 12 lsb gain error (3) gain error given for a 12-bit input code - - 0.5 % t settling (3) settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when dac_out reaches c load 50 pf, r load 5 k -3 4 s docid025146 rev 6 109/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 33. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.20 comparator characteristics update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) c load 50 pf, r load 5 k -- 1ms/s t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) c load 50 pf, r load 5 k - 6.5 10 s psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement c load = 50 pf, no r load 5 k , - ?67 ?40 db 1. guaranteed by design. 2. quiescent mode refers to the state of the dac a keepi ng steady value on the output, so no dynamic consumption is involved. 3. guaranteed by characterization results. table 69. dac characteristics (continued) symbol parameter conditions min typ max unit % x i i h u h g 1 r q e x i i h u h g ' $ & ' $ & b 2 8 7 [ % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u 5 / & / 0 6 9 table 70. comparator characteristics (1)(2) symbol parameter conditions min. typ. max. unit v dda analog supply voltage - 2 - 3.6 v v in comparator input voltage range -0-v dda v v bg scaler input voltage - - v refinit - v sc scaler offset voltage - - 5 10 mv electrical characteristics stm32f301x6 stm32f301x8 110/135 docid025146 rev 6 figure 34. maximum v refint scaler startup time from power down t s_sc v refint scaler startup time from power down v refint scaler activation after device power on --1 (3) s next activations - - 0.2 ms t start comparator startup time v dda 2.7 v - - 4 s v dda < 2.7 v - - 10 t d propagation delay for 200 mv step with 100 mv overdrive v dda 2.7 v - 25 28 ns v dda < 2.7 v - 28 30 propagation delay for full range step with 100 mv overdrive v dda 2.7 v - 32 35 v dda < 2.7 v - 35 40 v offset comparator offset error v dda 2.7 v - 5 10 mv v dda < 2.7 v - - 25 tv offset total offset variation full temperature range - - 3 mv i dd(comp) comp current consumption - - 400 600 a 1. guaranteed by design. 2. the comparators do not have built-in hysteresis. 3. for more details and conditions, see figure 34: maximum vrefint scaler startup time from power down . table 70. comparator characteristics (1)(2) (continued) symbol parameter conditions min. typ. max. unit docid025146 rev 6 111/135 stm32f301x6 stm32f301x8 electrical characteristics 114 6.3.21 operational am plifier char acteristics table 71. operational amplifier characteristics (1) symbol parameter condi tion min typ max unit v dda analog supply voltage - 2.4 - 3.6 v cmir common mode input range - 0 - v dda v vi offset input offset voltage maximum calibration range 25c, no load on output. --4 mv all voltage/temp. - - 6 after offset calibration 25c, no load on output. --1.6 all voltage/temp. - - 3 vi offset input offset voltage drift - - 5 - v/c i load drive current - - - 500 a iddopamp consumption no load, quiescent mode - 690 1450 a cmrr common mode rejection ratio - - 90 - db psrr power supply rejection ratio dc 73 117 - db gbw bandwidth - - 8.2 - mhz sr slew rate - - 4.7 - v/s r load resistive load - 4 - - k c load capacitive load - - - 50 pf voh sat high saturation voltage (2) r load = min, input at v dda . v dda -100 - - mv r load = 20k, input at v dda . v dda -20 - - vol sat low saturation voltage (2) rload = min, input at 0v --100 rload = 20k, input at 0v. --20 ? m phase margin - - 62 - t offtrim offset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy ---2ms t wakeup wake up time from off state. c load 50 pf, r load 4 k , follower configuration -2.85s t s_opam_vout adc sampling time when reading the opamp output 400 - - ns electrical characteristics stm32f301x6 stm32f301x8 112/135 docid025146 rev 6 pga gain non inverting gain value - -2- - -4- -8- -16- r network r2/r1 internal re sistance values in pga mode (3) gain=2 - 5.4/5.4 - k gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error - -1% - 1% % i bias opamp input bias current - - - 0.2 (4) a pga bw pga bandwidth for different non inverting gain pga gain = 2, cload = 50pf, rload = 4 k -4- mhz pga gain = 4, cload = 50pf, rload = 4 k -2- pga gain = 8, cload = 50pf, rload = 4 k -1- pga gain = 16, cload = 50pf, rload = 4 k -0.5- v n voltage noise density @ 1khz, output loaded with 4 k -109- @ 10khz, output loaded with 4 k -43- 1. guaranteed by design. 2. the saturation voltage can also be limited by the i load (drive current). 3. r2 is the internal resistance between opamp output and opamp inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 4. mostly tta i/o leakage, when used in analog mode. table 71. operational amplifier characteristics (1) (continued) symbol parameter condi tion min typ max unit nv hz ----------- docid025146 rev 6 113/135 stm32f301x6 stm32f301x8 electrical characteristics 114 figure 35. opamp voltage noise versus frequency electrical characteristics stm32f301x6 stm32f301x8 114/135 docid025146 rev 6 6.3.22 temperature sensor characteristics 6.3.23 v bat monitoring characteristics table 72. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s table 73. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 74. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 2.2 - - s docid025146 rev 6 115/135 stm32f301x6 stm32f301x8 package information 131 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. package information stm32f301x6 stm32f301x8 116/135 docid025146 rev 6 7.1 wlcsp49 pac kage information figure 36. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. % r w w r p y l h z % x p s v l g h 6 l g h y l h z ) u r q w y l h z 7 r s y l h z : d i h u e d f n v l g h $ e d o o o r f d w l r q h ) * h h h ( ' $ $ ' h w d l o $ $ e e e = ' h w d l o $ u r w d w h g 6 h d w l q j s o d q h 1 r w h 1 r w h % x p s [ h h h = 2 u l h q w d w l r q u h i h u h q f h $ [ ' ( $ $ e $ ; - b 0 ( b 9 $ docid025146 rev 6 117/135 stm32f301x6 stm32f301x8 package information 131 figure 37. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint table 75. wlcsp49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 3.382 3.417 3.452 0.1331 0.1345 0.1359 e 3.116 3.151 3.186 0.1227 0.1241 0.1254 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - f - 0.5085 - - 0.0200 - g - 0.3755 - - 0.0148 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 0 6 9 ' v p ' s d g package information stm32f301x6 stm32f301x8 118/135 docid025146 rev 6 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 38. wlcsp49 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 76. wlcsp49 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 dpad 260 m max. (circular) 220 m recommended dsm 300 m min. (for 260 m diameter pad) pcb pad design non-solder mask defined via underbump allowed. 0 6 9 ' $ 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h : 8 8 3 5 h y l v l r q f r g h docid025146 rev 6 119/135 stm32f301x6 stm32f301x8 package information 131 7.2 lqfp64 package information figure 39. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 77. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package information stm32f301x6 stm32f301x8 120/135 docid025146 rev 6 figure 40. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 77. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid025146 rev 6 121/135 stm32f301x6 stm32f301x8 package information 131 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 41. lqfp64 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l f d w l r q 4 5 . ' 3 5 3 : 8 8 5 h y l v l r q f r g h ' d w h f r g h package information stm32f301x6 stm32f301x8 122/135 docid025146 rev 6 7.3 lqfp48 package information figure 42. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + docid025146 rev 6 123/135 stm32f301x6 stm32f301x8 package information 131 table 78. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 package information stm32f301x6 stm32f301x8 124/135 docid025146 rev 6 figure 43. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. a i d docid025146 rev 6 125/135 stm32f301x6 stm32f301x8 package information 131 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 44. lqfp48 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 4 5 . ' $ 5 3 : 8 8 3 l q l g h q w l i l f d w l r q 5 h y l v l r q f r g h ' d w h f r g h package information stm32f301x6 stm32f301x8 126/135 docid025146 rev 6 7.4 ufqfpn32 package information figure 45. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table: pin definitions. ! " ? - % ? 6 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' docid025146 rev 6 127/135 stm32f301x6 stm32f301x8 package information 131 figure 46. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. table 79. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d1 3.400 3.500 3.600 0.1339 0.1378 0.1417 d2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e1 3.400 3.500 3.600 0.1339 0.1378 0.1417 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 package information stm32f301x6 stm32f301x8 128/135 docid025146 rev 6 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 47. ufqfpn32 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. ' , 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h : 8 8 ' d w h f r g h 3 3 l q l g h q w l i l h u 0 6 9 docid025146 rev 6 129/135 stm32f301x6 stm32f301x8 package information 131 7.5 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 23: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.5.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 80. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient wcsp49 - 3.4 x 3.4 mm 49 thermal resistance junction-ambient ufqfn32 - 5 x 5 mm 37 package information stm32f301x6 stm32f301x8 130/135 docid025146 rev 6 7.5.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: ordering information . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm32f301x6 stm32f301x8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temper ature range will be best su ited to the application. the following examples show how to calculat e the temperature range needed for a given application. example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 3 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 2 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 3 8 ma 0.4 v + 2 20 ma 1.3 v = 61.6 mw this gives: p intmax = 175 mw and p iomax = 61.6 mw: p dmax = 175 + 61.6 = 236.6 mw thus: p dmax = 236.6 mw using the values obtained in table 80 t jmax is calculated as follows: ? for lqfp64, 45c/w t jmax = 82 c + (45c/w 236.6 mw) = 82c + 10.65 c = 92.65c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 6 (see section 8: ordering information ). docid025146 rev 6 131/135 stm32f301x6 stm32f301x8 package information 131 example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 9 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 9 8 ma 0.4 v = 28.8 mw this gives: p intmax = 70 mw and p iomax = 28.8 mw: p dmax = 70 + 28.8 = 98.8 mw thus: p dmax = 98.8 mw using the values obtained in table 80 t jmax is calculated as follows: ? for lqfp100, 45c/w t jmax = 115c + (45c/w 98.8 mw) = 115 c + 4.44c = 119.44c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: ordering information ). ordering information stm32f301x6 stm32f301x8 132/135 docid025146 rev 6 8 ordering information table 81. ordering information scheme example: stm32 f 301 k 8 t 6 xxx device family stm32 = arm ? -based 32-bit microcontroller product type f = general-purpose device subfamily 301 = stm32f301xx, 2.0 to 3.6 v operating voltage pin count k = 32 pins c = 48 or 49 pins r = 64 pins flash memory size 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory package t = lqfp y= wlcsp u= ufqfpn temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and reel docid025146 rev 6 133/135 stm32f301x6 stm32f301x8 revision history 134 9 revision history table 82. document revision history date revision changes 10-apr-2014 1 initial release. 13-may-2014 2 updated table 13: stm32f301x6/8 pin definitions . added the input voltage on boot0 pin in table 20: voltage characteristics . 02-dec-2014 3 applied the following changes: ? added ?interconnect matrix? to features , ? added the timers-related information in table 2: stm32f301x6/8 device features and peripheral counts , ? updated the number of comparators for 32-pin package in table 2: stm32f301x6/8 device features and peripheral counts ? updated figure 1: stm32f301x6/8 block diagram , ? updated section 3.5.1: power supply schemes and added table 3: external analog supply values for analog peripherals , ? added a table footnote about touch sensing sensitivity for pins pa4 and pa6 in table 13: stm32f301x6/8 pin definitions , ? renamed usartx_rts as usartx_rts_de where x=1, 2 or 3, ? updated i dd values at 48 mhz (supply current in run mode, executing from ram/external clock (hse bypass)) in table 29: typical and maximum current consumption from vdd supply at vdd = 3.6v , ? updated t wustop maximum values in table 38: low-power mode wakeup timings , ? updated figure 18: hsi oscillator accuracy characterization results for soldered parts and table 44: hsi oscillator characteristics , ? updated the supply current in stop mode values for t a =25 deg. celsius in table 31: typical and maximum vdd consumption in stop and standby modes , ? replaced all occurrences of v dda monitoring with v dda supervisor in section 6: electrical characteristics , ? added footnotes to figure : device marking , ? updated the marking information ( figure 38: wlcsp49 marking example (package top view) , figure 41: lqfp64 marking example (package top view) , figure 44: lqfp48 marking example (package top view) , figure 47: ufqfpn32 marking example (package top view) ). 09-feb-2015 4 updated: ? table 42: hse oscillator characteristics ? table 47: flash memory characteristics ? table 70: comparator characteristics added: ? figure 34: maximum vrefint scaler startup time from power down revision history stm32f301x6 stm32f301x8 134/135 docid025146 rev 6 04-jun-2015 5 updated: ? af9 value for pa1, pa3 and pa9 in table 14: alternate functions for port a , ? the structure of section 7: package information . 22-jul-2016 6 updated notes on: ? all document tables by removing the ?not tested in production? specification. ? table 13: stm32f301x6/8 pin definitions . ? table 20: voltage characteristics . ? table 70: comparator characteristics . ? figure 4: stm32f301x6/8 ufqfn32 pinout . ? figure 5: stm32f301x6/8 lqfp48 pinout . ? figure 6: stm32f301x6/8 lqfp64 pinout . ? figure 7: stm32f301x6/8 wlcsp49 ballout . ? figure 24: recommended nrst pin protection . ? figure 45: ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline . updated tables: ? updated v refint line on table 27: embedded internal reference voltage . ? updated ?conditions? column on table 43: lse oscillator characteristics (flse = 32.768 khz) . ? added cmir and t stab lines on table 64: adc characteristics . ? updated r load line on table 69: dac characteristics . ? updated voh sat and vol sat lines on table 71: operational amplifier characteristics . updated figures: ? figure 2: clock tree . ? figure 7: stm32f301x6/8 wlcsp49 ballout . ? figure 21: five volt tolerant (ft and ftf) i/o input characteristics - cmos port . ? figure 24: recommended nrst pin protection . added: ? table 39: wakeup time using usart updated name of section 8: ordering information table 82. document revision history (continued) date revision changes docid025146 rev 6 135/135 stm32f301x6 stm32f301x8 135 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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